In recent years, an interface (I/F) called as a “PCI express (PCI Express)” has been widely used in place of a PCI bus (Peripheral Component Interconnect bus). The PCI bus adopts a parallel transfer method, while the PCI express (PCI Express) adopts a serial transfer method. Although compatibility between the PCI bus and the PCI express (PCI Express) at physical level does not exists, communication protocol and so on are commonly used. In a transmission path (lane) with minimum configuration, which is used in the PCI express (PCI Express), full-duplex communication of 2.5 Gbps (Gigabit per second) in one-way and 5.0 Gbps in two-way is possible.
FIG. 1 shows an example of a conventional system configuration in executing an extended network service by a control server (controller). In the conventional system, only one CPU (Central Processing Unit) exists on the switching node, and processing related to all service protocols is executed in cooperation with the control server via the PCI express (PCI Express) as a serial transfer interface used to connect a network switch forwarding engine.
FIG. 2 shows an example of a configuration of the CPU on the conventional switching node. A module of processing related to the extended network service executed by the external control server and a module of processing related to a locally executed conventional network service are executed on the CPU as network protocol processing on an operating system.
In the software stack configuration configured on the conventional CPU as shown in FIG. 2, since only one CPU exists, the one CPU must address both the processing related to the conventional network service and the processing related to the extended network service.
Further, in the conventional system configuration, the PCI express (PCI Express) is an only interface between internal modules (CPU) and an external connection device (network switch forwarding engine) and therefore, internal modules struggle for resources, which requires distribution and priority control processing.
Further, since the PCI express (PCI Express) causes overhead at transmission/reception of a packet, high-speed packet transmission/reception cannot be disadvantageously achieved.
Moreover, when control of the PCI express (PCI Express) is delayed, overflow of a CPU-destined packet queue in the network switch forwarding engine, disposition of the packet and decline in the service quality occur.
Due to the above-mentioned problems, the conventional system configuration is configured on the assumption of processing related to the service protocol having a light load on the control interface and therefore, cannot realize a configuration that needs high-speed packet transmission/reception with the external control server.
Patent literature 1 (JPA 2005-317021) described PCI express (PCI Express). For example, a topology for the PCI express (PCI Express) included in a computing device includes a host bridge and some end points (that is, an I/O device) in addition to the CPU and a memory. The plurality of points are connected by means of a switch.
As a related technique, Patent literature 2 (JPA 2006-202210) discloses an information processing device, and a service publication method and a program. According to the related technique, a UPnP (Universal Plug and Play) device announces the existence of the device (the equipment) to a UPnP control point according to an SSDP (Simple Service Discovery Protocol), and publicizes device description and service description, which are described in an XML (Extensible Markup Language) format. The UPnP control point finds UPnP device and service according to the SSDP, and controls an action of each service by a call based on an SOAP (Simple Object Access Protocol). A change of a state of the UPnP service is notified to the UPnP control point that reads an event notification based on a GENA (Generic Event Notification Architecture).
As a related technique, Patent literature 3 (JPA 2007-219873) discloses a switch and a network bridge device. According to the related technique, a route complex receives a command from a CPU and transfers peer to peer communication between the CPU and a peripheral device, and peer to peer communication between a memory and the peripheral device. At this time, the route complex and the peripheral device are communicated with each other by using a packet (TLP: Transaction Layer Packet) of the PCI express (PCI Express).